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august 2003 1 ks8995e ks8995e micrel ks8995e 5-port 10/100 integrated switch with phy and frame buffer rev. 1.10 general descriptionthe ks8995e contains five 10/100 physical layer transceiv- ers, five mac (media access control) units with an integrated layer 2 switch. the device runs in two modes. the first mode is a five port integrated switch and the second is as a five port switch with the fifth port decoupled from the physical port. in this mode access to the fifth mac is provided using an mii (media independent interface). useful configurations include a stand alone five port switch as well as a four port switch with a routing element connected to the extra mii port. the additional port is also useful for a public network interfacing. the ks8995e is designed to reside in an unmanaged design not requiring processor intervention. this is achieved through i/o strapping or eeprom programming at system reset time. micrel, inc. ? 1849 fortune drive ? san jose, ca 95131 ? usa ? tel + 1 (408) 944-0800 ? fax + 1 (408) 944-0970 ? http://www.mic rel.com functional diagram physical transceiver 1 mac 1 look up engine (1k entries) sram buffers (32kx32) mii / sni(exclusive) external interface physical transceiver 2 mac 2 physical transceiver 3 mac 3 physical transceiver 4 mac 4 physical transceiver 5 mac 5 fifo and flow control queue management buffer management led and programming interface mrxd[3:0]mrxdv mcol mtxd[3:0] mtxen mtxer mii_clk rxp[1], rxm[1] rxp[2], rxm[2] rxp[3], rxm[3] rxp[4], rxm[4] rxp[5], rxm[5] txp[1], txm[1] txp[2], txm[2] txp[3], txm[3] txp[4], txm[4] txp[5], txm[5] led[1][3:0]led[2][3:0] led[3][3:0] led[4][3:0] led[5][3:0] mrxd[0]mrxdv mcol mtxd[0] mtxen mii_clk s n i m ii eeprom interface sclsda on the media side, the ks8995e supports 10baset,100basetx and 100basefx as specified by the ieee 802.3 committee. physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. the major enhancements from the ks8995 to the ks8995e are support for vlan, traffic priority queuing, eeprom programming for expanded control, mdi/mdi-x auto cross- over. data sheets and support documentation can be found on micrels web site at www.micrel.com. downloaded from: http:///
ks8995e micrel ks8995e 2 august 2003 ordering information part number temperature range package ks8995e 0 c to +70 c 128-pin pqfp features ? 5-port 10/100 integrated switch with physical layer transceivers ? 128k byte of sram on chip for frame buffering ? 1.4gbps high performance memory bandwidth ? 10baset, 100basetx and 100basefx modes of operation ? superior analog technology for reduced power and die size ? supports port based vlan ? qos feature!! supports diffserv priority, 802.1p based priority or port-based priority ? support for utp or fiber installations ? indicators for link, activity, full/half-duplex and speed ? unmanaged operation via strapping or eeprom at system reset time ? hardware based 10/100, full/half, flow control and auto- negotiation ? individual port forced modes (full-duplex, 100basetx) when auto-negotiation is disabled ? wire speed reception and transmission ? integrated address look-up engine, supports 1k abso- lute mac addresses ? automatic address learning, address aging and address migration ? broadcast storm protection ? full duplex ieee 802.3x flow control ? half duplex back pressure flow control ? comprehensive led support ? external mac interface (mii or sni) for router applica- tions ? supports mdi/mdi-x auto crossover ? single 2.5v power supply ? 700ma (1.75w) including physical transmit drivers ? commercial temperature range: 0 c to +70 c ? available in 128-pin pqfp package downloaded from: http:///
august 2003 3 ks8995e ks8995e micrel revision history revision date summary of changes 1.00 7/28/00 document origination. 1.01 8/21/00 change led programming. 1.02 10/30/00 update voltage ratings. 1.03 2/02/01 update transformer recommendations. 1.04 3/27/01 update maximum frame length values. 1.05 4/20/01 correct timing information. 1.06 5/03/01 correct i/o definition. 1.07 5/11/01 add mdi/mdi-x description. 1.08 7/25/01 update timing information. 1.09 8/09/01 add appendix d & mii timing. add 10basetx power dissipation. 1.10 8/29/03 convert to new format. downloaded from: http:///
ks8995e micrel ks8995e 4 august 2003 table of contents system level applications ...................................................................................................... ........................................................ 6 pin description .............................................................................................................................................................................. 7 i/o grouping ............................................................................................................................... ............................................. 11 i/o descriptions ............................................................................................................................... ............................................. 12 pin configuration .............................................................................................................. ............................................................. 16 functional overview: physical layer transceiver ................................................................................. .................................... 17 100basetx transmit ............................................................................................................. .................................................. 17 100basetx receive .............................................................................................................. .................................................. 17 pll clock synthesizer .......................................................................................................... .................................................. 17 scrambler/de-scrambler (100basetx only) ........................................................................................ .................................... 17 100basefx operation ............................................................................................................ .................................................. 17 100basefx signal detection ..................................................................................................... .............................................. 17 100basefx far end fault ........................................................................................................ ............................................... 17 10baset transmit ............................................................................................................... .................................................... 17 10baset receive ................................................................................................................ .................................................... 17 power management ............................................................................................................... ................................................. 18 power save mode ................................................................................................................ ........................................... 18 mdi/mdi-x auto crossover ....................................................................................................... .............................................. 18 auto-negotiation ...................................................................................................................................................................... 18 functional overview: switch core ............................................................................................... ................................................ 19 address look up ................................................................................................................ ..................................................... 19 learning .......................................................................................................................................................................... 19 migration ......................................................................................................................................................................... 19 aging ............................................................................................................................................................................ 19 forwarding ...................................................................................................................................................................... 19 switching engine ............................................................................................................... ...................................................... 19 mac (media access controller) operation ........................................................................................ ..................................... 19 inter packet group ............................................................................................................. ............................................. 19 back off algorithm ............................................................................................................. ...................................................... 19 late collision ................................................................................................................. .......................................................... 19 illegal frame .................................................................................................................. .......................................................... 19 flow control ................................................................................................................... ......................................................... 19 half-duplex back pressure ...................................................................................................... ....................................... 19 broadcast storm protection ..................................................................................................... ................................................ 19 mii interface operation ........................................................................................................ .......................................................... 21 sni interface (7-wire) operation ............................................................................................... .................................................... 22 8995e improvements ............................................................................................................. ........................................................ 22 priority schemes ............................................................................................................... ...................................................... 22 per port method ................................................................................................................ ...................................................... 22 802.1p method .................................................................................................................. ....................................................... 22 ipv4 dscp method ............................................................................................................... .................................................. 22 other priority considerations .................................................................................................. ................................................ 22 vlan operations ................................................................................................................ ........................................................... 23 other programmable features .................................................................................................... ................................................. 24 eeprom operations .............................................................................................................. ........................................................ 24 compatibility with ks8995 ...................................................................................................... ...................................................... 24 downloaded from: http:///
august 2003 5 ks8995e ks8995e micrel eeprom memory map .............................................................................................................. ..................................................... 25 priority classification control C 802.1p tag field ............................................................................. ....................................... 25 control register 1 ............................................................................................................. ....................................................... 25 control register 2 ............................................................................................................. ....................................................... 25 control register 3 ............................................................................................................. ....................................................... 26 control register 4 ............................................................................................................. ....................................................... 26 control register 5 ............................................................................................................. ....................................................... 26 port 1 vlan mask register ...................................................................................................... ............................................... 27 port 2 vlan mask register ...................................................................................................... ............................................... 27 port 3 vlan mask register ...................................................................................................... ............................................... 27 port 4 vlan mask register ...................................................................................................... ............................................... 28 port 5 vlan mask register ...................................................................................................... ............................................... 28 port 1 vlan tag insertion value register ....................................................................................... ....................................... 28 port 2 vlan tag insertion value register ....................................................................................... ....................................... 28 port 3 vlan tag insertion value register ....................................................................................... ....................................... 29 port 4 vlan tag insertion value register ....................................................................................... ....................................... 29 port 5 vlan tag insertion value register ....................................................................................... ....................................... 29 diff serv code point register .................................................................................................................................................. 29 station mac address registers (all ports C mac control frames only) ............................................................ ....................... 29 absolute maximum ratings ....................................................................................................... ................................................... 30 operating ratings .............................................................................................................. ............................................................ 30 electrical characteristics ..................................................................................................... ......................................................... 30 timing diagrams ................................................................................................................ ............................................................ 32 reference circuit .............................................................................................................. ............................................................. 36 4b/5b coding ............................................................................................................................... ............................................. 37 mlt coding ............................................................................................................................... ............................................. 38 802.1q vlan and 802.1p priority frame .......................................................................................... ............................................ 39 selection of isolation transformers ............................................................................................ ................................................. 40 selection of reference crystals ................................................................................................ ................................................... 40 package outline and dimensions ................................................................................................. ............................................... 41 downloaded from: http:///
ks8995e micrel ks8995e 6 august 2003 system level applications the ks8995e can be configured to fit either in a five port 10/ 100 application or as a four port 10/100 network interface with an extra mii / sni port. this mii / sni port can be connected to an external processor and used for routing purposes or public network access. the major benefits of using theks8995e are the lower power consumption, unmanaged operation, flexible configuration, built in frame buffering, vlan abilities and traffic priority control. two such applica- tions are depicted below. ks8995e 5-port switch with phy ks8995e 5 port switch with phy routing engine 5x transformer or fiber interface 4x transformer or fiber interface public network access 5-port stand alone 4-port with public network interface or mii or sni figure 1. ks8995e applications downloaded from: http:///
august 2003 7 ks8995e ks8995e micrel pin description pin number pin name type (note 1) port pin function 1 n/c not used - float for normal operation (no connect) 2 txp[1] o 1 physical transmit signal + (differential) 3 txm[1] o 1 physical transmit signal - (differential) 4 gnd_tx[1] gnd 1 ground for transmit circuitry 5 vdd_tx[1:2] p 2.5v for transmit circuitry 6 gnd_tx[2] gnd 2 ground for transmit circuitry 7 txp[2] o 2 physical transmit signal + (differential) 8 txm[2] o 2 physical transmit signal - (differential) 9 n/c not used - float for normal operation (no connect) 10 vdd_rx[2] p 2 2.5v for equalizer 11 rxp[2] i 2 physical receive signal + (differential) 12 rxm[2] i 2 physical receive signal - (differential) 13 gnd_rx[2] gnd 2 ground for equalizer 14 vdd_bg p 2.5v for analog circuitry 15 iset o set physical transmit output current 16 gnd_bg gnd ground for analog circuitry 17 gnd_rx[3] gnd 3 ground for equalizer 18 rxp[3] i 3 physical receive signal + (differential) 19 rxm[3] i 3 physical receive signal - (differential) 20 vdd_rx[3] p 3 2.5v for equalizer 21 n/c not used - float for normal operation (no connect) 22 txp[3] o 3 physical transmit signal + (differential) 23 txm[3] o 3 physical transmit signal - (differential) 24 gnd_tx[3] gnd 3 ground for transmit circuitry 25 vdd_tx[3:4] p 2.5v for transmit circuitry 26 gnd_tx[4] gnd 4 ground for transmit circuitry 27 txp[4] o 4 physical transmit signal + (differential) 28 txm[4] o 4 physical transmit signal - (differential) 29 n/c not used - float for normal operation (no connect) 30 vdd_rx[4] p 4 2.5v for equalizer 31 rxp[4] i 4 physical receive signal + (differential) 32 rxm[4] i 4 physical receive signal - (differential) 33 gnd_rx[4] gnd 4 ground for equalizer 34 gnd_rx[5] gnd 5 ground for equalizer 35 rxp[5] i 5 physical receive signal + (differential) 36 rxm[5] i 5 physical receive signal - (differential) 37 vdd_rx[5] p 5 2.5v for equalizer 38 gnd_ana gnd analog ground note 1. p = power supplygnd = ground i = input o = output i/o = bi-directional downloaded from: http:///
ks8995e micrel ks8995e 8 august 2003 pin number pin name type (note 1) port pin function 39 n/c not used - float for normal operation (no connect) 40 txp[5] o 5 physical transmit signal + (differential) 41 txm[5] o 5 physical transmit signal - (differential) 42 gnd_tx[5] gnd 5 ground for transmit circuitry 43 vdd_tx[5] p 5 2.5v for transmit circuitry 44 fxsd[2] i 2 fiber signal detect 45 fxsd[3] i 3 fiber signal detect 46 fxsd[4] i 4 fiber signal detect 47 fxsd[5] i 5 fiber signal detect 48 gnd_rcv[5] gnd 5 ground for clock recovery circuitry 49 vdd_rcv[5] p 5 2.5v for clock recovery circuitry 50 vdd_rcv[4] p 4 2.5v for clock recovery circuitry 51 gnd_rcv[4] gnd 4 ground for clock recovery circuitry 52 gnd_rcv[3] gnd 3 ground for clock recovery circuitry 53 vdd_rcv[3] p 3 2.5v for clock recovery circuitry 54 test[1] i factory test pin C float for normal operation 55 test[2] i factory test pin C float for normal operation 56 scl o clock for eeprom 57 sda i/o serial data for eeprom 58 vdd p 2.5v for core digital circuitry 59 gnd gnd ground for digital circuitry 60 mtxen i 5 mii transmit enable 61 mtxd[3] i 5 mii transmit bit 3 62 mtxd[2] i 5 mii transmit bit 2 63 mtxd[1] i 5 mii transmit bit 1 64 mtxd[0] i 5 mii transmit bit 0 65 mtxer i 5 mii transmit error 66 mii_clk o 5 mii clock 67 mrxdv o 5 mii receive data valid 68 mrxd[3] o 5 mii receive bit 3 69 mrxd[2] o 5 mii receive bit 2 70 mrxd[1] o 5 mii receive bit 1 71 mrxd[0] o 5 mii receive bit 0 72 mcol o mii collision detect 73 vdd-io p 2.5v or 3.3v for mii interface 74 gnd gnd ground for digital circuitry 75 p5ext i 5 external port 5 selector 76 p5sni i 5 external port 5 mode selector note 1. p = power supplygnd = ground i = input o = output i/o = bi-directional downloaded from: http:///
august 2003 9 ks8995e ks8995e micrel pin number pin name type (note 1) port pin function 77 modesel[3] i selects led and test modes 78 modesel[2] i selects led and test modes 79 vdd p 2.5v for core digital circuitry 80 gnd gnd ground for digital circuitry 81 modesel[1] i selects led and test modes 82 modesel[0] i selects led and test modes 83 testen i factory test pin C tie to ground for normal operation 84 scanen i factory test pin C tie to ground for normal operation 85 rst# i reset C active low 86 led[1][3] i/o 1 led indicator 3 87 led[1][2] i/o 1 led indicator 2 88 led[1][1] i/o 1 led indicator 1 89 led[1][0] i/o 1 led indicator 0 90 led[2][3] i/o 2 led indicator 3 91 led[2][2] i/o 2 led indicator 2 92 led[2][1] i/o 2 led indicator 1 93 led[2][0] i/o 2 led indicator 0 94 vdd p 2.5v for core digital circuitry 95 gnd gnd ground for digital circuitry 96 led[3][3] i/o 3 led indicator 3 97 led[3][2] i/o 3 led indicator 2 98 led[3][1] i/o 3 led indicator 1 99 led[3][0] i/o 3 led indicator 0 100 vdd-io p 2.5v or 3.3v for mii interface 101 gnd gnd ground for digital circuitry 102 led[4][3] i/o 4 led indicator 3 103 led[4][2] i/o 4 led indicator 2 104 led[4][1] i/o 4 led indicator 1 105 led[4][0] i/o 4 led indicator 0 106 led[5][3] i/o 5 led indicator 3 107 led[5][2] i/o 5 led indicator 2 108 led[5][1] i/o 5 led indicator 1 / 109 led[5][0] i/o 5 led indicator 0 / 110 vdd p 2.5v for core digital circuitry 111 gnd gnd ground for digital circuitry 112 x2 o connect to crystal 113 x1 i crystal or clock input 114 vdd_pll p 2.5v for phase locked loop circuitry 115 gnd_pll gnd ground for phase locked loop circuitry note 1. p = power supplygnd = ground i = input o = output i/o = bi-directional downloaded from: http:///
ks8995e micrel ks8995e 10 august 2003 pin number pin name type (note 1) port pin function 116 gnd_rcv[2] gnd 2 ground for clock recovery circuitry 117 vdd_rcv[2] p 2 2.5v for clock recovery circuitry 118 vdd_rcv[1] p 1 2.5v for clock recovery circuitry 119 gnd_rcv[1] gnd 1 ground for clock recovery circuitry 120 mux[2] i factory test pin C float for normal operation 121 mux[1] i factory test pin C float for normal operation 122 fxsd[1] i fiber signal detect 123 aout o factory test output C float for normal operation 124 gnd_rx[1] gnd 1 ground for equalizer 125 rxp[1] i 1 physical receive signal + (differential) 126 rxm[1] i 1 physical receive signal - (differential) 127 vdd_rx[1] p 1 2.5v for equalizer 128 gnd_ana gnd analog ground note 1. p = power supplygnd = ground i = input o = output i/o = bi-directional downloaded from: http:///
august 2003 11 ks8995e ks8995e micrel i/o grouping group name description phy physical interface mii media independant interface sni serial network interface ind led indicators up unmanaged programmable ctrl control and miscellaneous test test (factory) pwr/gnd power and ground downloaded from: http:///
ks8995e micrel ks8995e 12 august 2003 i/o descriptions group i/o names active status description phy rxp[1:5] analog differential inputs (receive) for connection to media (transformer or fiber module) rxm[1:5] txp[1:5] analog differential outputs (transmit) for connection to media (transformer or fiber module) txm[1:5] fxsd[1:5] h fiber signal detect - connect to fiber signal detect output on fiber module. tie low for 100tx mode. iset analog transmit current set. connecting an external reference resistor to set transmitter output current. this pin connects a 1% 3k resistor if a transformer of turns ratio of 1:1 is used. mii mrxd[0:3] h four bit wide data bus for receiving mac frames mrxdv h receive data valid mcol h receive collision detection mtxd[0:3] h four bit wide data bus for transmitting mac frames mtxen h transmit enable mtxer h transmit error mii_clk clock mii interface clock sni mtxd[0] h serial transmit data mtxen h transmit enable mrxd[0] h serial receive data mrxdv h receive carrier sense/data valid mcol h collision detection mii_clk clock sni interface clock ind led[1:5][0] l output (after reset) mode 0: speed (on = 100/off = 10) mode 1: speed (on = 100/off = 10) mode 2: speed (on = 100/off = 10) mode 3: speed (on = 100/off = 10) led[1:5][1] l output (after reset) mode 0: full duplex (on = full/off = half) mode 1: link (on = connected/off = not connected) mode 2: link (on = connected/off = not connected) mode 3: reserved led[1:5][2] l output (after reset) mode 0: collision (on = collision / off = no collision) mode 1: transmit activity (on during transmission) mode 2: full duplex + collision (constant on = full-duplex / intermittent on = collision/off = half-duplex with no collision) mode 3: full duplex + collision (constant on = full-duplex / intermittent on = collision/off = half-duplex with no collision) led[1:5][3] l output (after reset) mode 0: link + activity mode 1: receive activity (on = receiving/off = not receiving) mode 2: activity (on = transmit or receive activity/off = no activity) mode 3: link + activity note: mode is set by modesel[3:0] ; please see description in up (unmanaged programming) section. downloaded from: http:///
august 2003 13 ks8995e ks8995e micrel group i/o names active status description (note 1) up modesel[3:0] h mode select at reset time. led mode is selected by using the table below. note that under normal operation modesel[3:2] must be tied low. modesel 3 2 1 0 operation 0 0 0 0 led mode 0 0 0 0 1 led mode 1 0 0 1 0 led mode 2 0 0 1 1 led mode 3 0 1 0 0 used for factory testing 0 1 0 1 used for factory testing 0 1 1 0 used for factory testing 0 1 1 1 used for factory testing 1 0 0 0 used for factory testing 1 0 0 1 used for factory testing 1 0 1 0 used for factory testing 1 0 1 1 used for factory testing 1 1 0 0 used for factory testing 1 1 0 1 used for factory testing 1 1 1 0 used for factory testing 1 1 1 1 used for factory testing led[1][3] programs flow control on all phy ports at reset time. d = no flow control f/u = flow control led[1][2] programs flow control on the external mac port at reset time. d = no flow control u = flow control led[1][1:0] programs buffer allocation per port at reset time. use the following table to select the option:led[1] 0 1 description d d 205 buffers max per port (default) d u 512 buffers max per port u d 768 buffers max per port u u 512 buffers (adaptive) per port led[2][3] programs mac address aging in the address look-up table at reset time. aging eliminates old entries from the table.d = no aging f/u = 5 minute aging led[2][2] pull-down for normal operation. led[2][1] programs back pressure in half-duplex at reset time. d = no back pressure f/u = back pressure enabled led[2][0] programs aggressive back off in half-duplex at reset time. d = standard back off f/u = aggressive mode enabled led[3][3] programs no excessive collision drop at reset time. d = drop after 16 collisions f/u = no drop after 16 collisions led[3][2] programs a limit for broadcast frames at reset time. d = no limitu = 25% - 3% limit of broadcast frames note: eeprom programming can limit broadcast frames at 25%, 12%, 6% or 3%. see eeprom register 7 bits 7-6. note 1. all unmanaged programming takes place at reset time only. for unmanaged programming: f = float, d = pull-down, u = pull-up. see reference circuits section. downloaded from: http:///
ks8995e micrel ks8995e 14 august 2003 group i/o names active status description (note 1) led[3][1:0] programs force 100basetx / 10baset mode at reset time. disable auto-negotiation led[4][3:1] to use this force mode. use the table below to set this mode on the appropriate port. signal port force 10baset force 100basetx auto-negotiation w/o auto-negotiation w/o auto-negotiation enabled led[3][1] 5 d u f led[3][0] 4 d u f led[4][3] 3 d u f led[4][2] 2 d u f led[4][1] 1 d u f led[4][0] programs force full / half-duplex mode at reset time. disable auto-negotiation to use led[5][3:0] this force mode. use the table below to set this mode on the appropriate port. signal port force half-duplex force full-duplex auto-negotiation w/o auto-negotiation w/o auto-negotiation enabled led[4][0] 5 d u f led[5][3] 4 d u f led[5][2] 3 d u f led[5][1] 2 d u f led[5][0] 1 d u f mrxd[0:3] programs auto-negotiation enable / disable at reset time. use the table below to set mcol this mode on the appropriate port. signal port enable disable auto-negotiation auto-negotiation mrxd[3] 5 d u mrxd[2] 4 d u mrxd[1] 3 d u mrxd[0] 2 d u mcol 1 d u note 1. to use external mii on port 5 disable auto-negotiation by pulling mrxd[3] up. note 2. use the disable auto-negotiation mode in conjunction with force 10/100 and force full/half-duplex to get the desired configuration. see above descriptions for force modes. ctrl p5ext h port 5 external selection. d = 5 port is mode u = external mac interface enabled and no longer connected to internal port 5 phy. p5sni h port 5 interface protocol. this is only relevant when p5ext is tied high. d = mii interface u = sni interface x1 clock external crystal or clock input. x2 clock used when other polarity of crystal is needed. this is unused for a normal clock input. scl clock clock for eeprom. sda serial data for eeprom. rst# l system reset. test testen h factory test input: tie to ground for normal operation. scanen h factory test input: tie to ground for normal operation. mux[1:2] h factory test input: leave open. aout h factory test output: leave open. test[1:2] h factory test inputs: leave open. note 1. all unmanaged programming takes place at reset time only. for unmanaged programming: f = float, d = pull-down, u = pull-up. see reference circuits section. downloaded from: http:///
august 2003 15 ks8995e ks8995e micrel group i/o names active status description pwr vdd-rx[1:5] 2.5v for equalizer. gnd-rx[1:5] ground for equalizer. vdd-tx[1:2] 2.5v for transmit circuitry. vdd-tx[3:4] 2.5v for transmit circuitry. vdd-tx[5] 2.5v for transmit circuitry. gnd-tx[1:5] ground for transmit circuitry. vdd-rcv[1:5] 2.5v for clock recovery circuitry. gnd-rcv[1:5] ground for clock recovery. vdd-pll 2.5v for phase locked loop circuitry. gnd-pll ground for phase locked loop circuitry. gnd-ana analog ground. vdd_bg 2.5v for analog circuits. gnd-bg analog ground. vdd 2.5v for core digital circuitry. vdd-io 2.5v or 3.3v for mii interface. gnd ground for digital circuitry. downloaded from: http:///
ks8995e micrel ks8995e 16 august 2003 pin configuration nc txp[1] txm[1] gnd_tx[1] vdd_tx[1:2] gnd_tx[2] txp[2] txm[2] nc vdd_rx[2] rxp[2] rxm[2] gnd_rx[2] vdd_bg iset gnd_bg gnd_rx[3] rxp[3] rxm[3] vdd_rx[3] nc txp[3] txm[3] gnd_tx[3] vdd_tx[3:4] gnd_tx[4] txp[4] txm[4] nc vdd_rx[4] rxp[4] rxm[4] gnd_rx[4]gnd_rx[5] rxp[5] rxm[5] vdd_rx[5] gnd_ana led[4][3]gnd vdd_io led[3][0] led[3][1] led[3][2] led[3][3] gnd vdd led[2][0] led[2][1] led[2][2] led[2][3] led[1][0] led[1][1] led[1][2] led[1][3] rst# scanen testen modesel[0] modesel[1] gnd vdd modesel[2] modesel[3] p5sni p5ext gnd vdd_io mcol mrxd[0] mrxd[1] mrxd[2] mrxd[3] mrxdv mii_clk mtxer mtxd[0]mtxd[1] mtxd[2] mtxd[3] mtxen gnd vdd sda scl test[2] test[1] vdd_rcv[3] gnd_rcv[3] gnd_rcv[4] vdd_rcv[4] vdd_rcv[5] gnd_rcv[5] fxsd[5] fxsd[4] fxsd[3] fxsd[2] vdd_tx[5] gnd_tx[5] txm[5] txp[5] nc led[4][2]led[4][1] led[4][0] led[5][3] led[5][2] led[5][1] led[5][0] vdd gnd x2x1 vdd_pll gnd_pll gnd_rcv[2] vdd_rcv[2]vdd_rcv[1] gnd_rcv[1] mux[2]mux[1] fxsd[1] aout gnd_rx[1] rxp[1] rxm[1] vdd_rx[1] gnd_ana 65 39 1 103 128-pin pqfp (pq) downloaded from: http:///
august 2003 17 ks8995e ks8995e micrel functional overview: physical layer transceiver 100basetx transmit the 100basetx transmit function performs parallel to serial conversion, 4b/5b coding, scrambling, nrz to nrzi conversion, mlt3 encoding and transmission. the circuit starts with a parallel to serial conversion, which converts the rmii or smii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz to nrzi format, then transmitted in mlt3 current output. the output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4 ns and complies to the ansi tp-pmd standard regarding amplitude balance, overshoot and timing jitters. the wave-shaped 10basetoutput is also incorporated into the 100basetx transmitter. 100basetx receive the 100basetx receiver function performs adaptive equalization, dc restoration, mlt3 to nrzi conversion, data and clock recovery, nrzi to nrz conversion, de-scrambling, 4b/5b decoding and serial to parallel conversion. the receiving side starts with the equalization filter to compensate inter-symbol interference (isi) over the twisted pair cable. since the amplitude los s and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize theperformance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and can self adjust against the environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the rmii or smii formats and provided as the input data to the mac. pll clock synthesizer the ks8995e generates 125mhz, 42mhz, 25mhz and 10mhz clocks for system timing. internal clocks are generated from an external 25mhz crystal. scrambler/de-scrambler (100basetx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. the data is scrambled by the use of an 11-bit wide linear feedback shift register (lfsr). this can generate a 2047-bit non-repetit ive sequence. the receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.100basefx operation 100basefx operation is very similar to 100basetx operation with the differences being that the scrambler / de-scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100basefx signal detection the physical port runs in 100basefx mode if fxsdx >0.6v. this signal is referenced to vrefx which is set at 1/2 vdd but can be overridden by an external level. vrefx can be connected to the minus signal of a differential pair coming from the fiber module ( plus connects to fxsdx) used to convey signal detect. when fxsdx is below 0.6v then 100basefx mode is disabled.100basefx far end fault far end fault occurs when the signal detection is logically false from the receive fiber module. when this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. 10baset transmit the output 10baset driver is incorporated into the 100baset driver to allow transmission with the same magnetics. they are internally wave-shaped and pre-emphasized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental when driven by an all-ones manchester-encoded signal. 10baset receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. asquelch circuit rejects signals with levels less than 400mv or with short pulse widths in order to prevent noises at the rxp or rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signa l and the ks8995e decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. downloaded from: http:///
ks8995e micrel ks8995e 18 august 2003 power management power save mode the ks8995e will turn off everything except for the energy detect and pll circuits when the cable is not installed on anindividual port basis. in other words, the ks8995e will shutdown most of the internal circuits to save power if there is no lin k. mdi/mdi-x auto crossoverthe ks8995e supports mdi/mdi-x auto crossover. this facilitates the use of either a straight connection cat-5 cable or a crossover cat-5 cable. the auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the micrel device. this can be highly useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. the auto mdi/mdi-x is achieved by the micrel device listening for the far end transmission channel and assigning transmit/ receive pairs accordingly. auto-negotiation the ks8995e conforms to the auto-negotiation protocol as described by the 802.3 committee. auto-negotiation allows utp (unshielded twisted pair) link partners to select the best common mode of operation. in auto-negotiation the link partners advertise capabilities across the link to each other. if auto-negotiation is not supported or the link partner to the ks8995e i s forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. this is known as parallel modebecause while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fix ed signal protocol.the flow for the link set up is depicted below. start auto negotiation force link setting listen for 10baset link pulses listen for 100basetx idles attempt auto-negotiation link mode set bypass auto-negotiation and set link mode link mode set ? parallel operation join flow no yes yes no figure 2. auto-negotiation downloaded from: http:///
august 2003 19 ks8995e ks8995e micrel functional overview: switch core address look up the internal look-up table stores mac addresses and their associated information. it contains 1k full cam with 48-bit address plus switching information. the ks8995e is guaranteed to learn 1k addresses and distinguishes itself from hash-based look- up tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal look-up engine will update its table with a new entry if the following conditions are met: ? the received packet s sa does not exist in the look-up table. ? the received packet is good; the packet has no receiving errors, and is of legal length. the look-up engine will insert the qualified sa into the table, along with the port number, time stamp. if the table is full, the last entry of the table will be deleted first to make room for the new entry. migrationthe internal look-up engine also monitors whether a station is moved. if it happens, it will update the table accordingly. migration happens when the following conditions are met: ? the received packet s sa is in the table but the associated source port information is different. ? the received packet is good; the packet has no receiving errors, and is of legal length. the look-up engine will update the existing record in the table with the new source port information.aging the look-up engine will update time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look-up engine will then remove the record f rom the table. the look-up engine constantly performs the aging process and will continuously remove aging records. the agingperiod is 300 seconds. this feature can be enabled or disabled by external pull-up or pull-down resistors. forwarding the ks8995e will forward packets as follows: ? if the da look-up results is a match , the ks8995e will use the destination port information to determine where the packet goes. ? if the da look-up result is a miss , the ks8995e will forward the packet to all other ports except the port that received the packet. ? all the multicast and broadcast packets will be forwarded to all other ports except the source port. the ks8995e will not forward the following packets: ? error packets. these include framing errors, fcs errors, alignment errors, and illegal size packet errors. ? 802.3x pause frames. the ks8995e will intercept these packets and do the appropriate actions. ? local packets. based on destination address (da) look-up. if the destination port from the look-up table matches the port where the packet was from, the packet is defined as local. switching enginethe ks8995e has a very high performance switching engine to move data to and from the mac s, packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency.the ks8995e has in internal buffer for frames that is 32kx32 (128kb). this resource is shared between the five ports. buffer sizing per port can be programmed at system reset time by using the unmanaged program mode (i/o strapping). each buffer is sized at 128b and therefore there are a total of 1024 buffers available. a per port maximum can be set at 205 (equal allocation), 512 or 768. there is also an adaptive 512 size mode that reacts to port traffic. mac (media access controller) operation the ks8995e strictly abides by ieee 802.3 standard to maximize compatibility. inter packet gap (ipg) if a frame is successfully transmitted, the 96-bit time ipg is measured between the two consecutive mtxen. if the currentpacket is experiencing collision, the 96-bit time ipg is measured from mcrs and the next mtxen. backoff algorithm the ks8995e implements the ieee std 802.3 binary exponential back-off algorithm, and optional aggressive mode back off. after 16 collisions, the packet will be optionally dropped depending on the chip configuration. downloaded from: http:///
ks8995e micrel ks8995e 20 august 2003 late collisionif a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. illegal frames the ks8995e discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes. since the ks8995e supports vlan tags, the maximum sizing is adjusted when these tags are present. see the eeprom section for programming options.flow control the ks8995e supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ks8995e receives a pause control frame, the ks8995e will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (being flow controlled), only flow control packets from the ks8995e will be transmitted. on the transmit side, the ks8995e has intelligent and efficient ways to determine when to invoke flow control. the flow contro l is based on availability of the system resources, including available buffers, available transmit queues and available receivequeues. the ks8995e will flow control a port, which just received a packet, if the destination port resource is being used up. the ks8995e will issue a flow control frame (xoff), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ks8995e will send out the other flow control frame (xon) with zero pause time to turn off the flo w control (turn on transmission to the port). a hysterisis feature is provided to prevent flow control mechanism from being activ ated and deactivated too many times.the ks8995e will flow control all ports if the receive queue becomes full. half duplex back pressure half duplex back pressure option (note: not in 802.3 standards) is also provided. the activation and deactivation conditionsare the same as the above in full-duplex mode. if back pressure is required, the ks8995e will send preambles to defer other stations transmission (carrier sense deference). to avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. if the port has packets to send during a back pressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. if there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generatedimmediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. broadcast storm protection the ks8995e has an intelligent option to protect the switch system from receiving too many broadcast packets. broadcast packets will be forwarded to all ports except the source port, and thus will use too many switch resources (bandwidth and available space in transmit queues). the ks8995e will discard broadcast or multicast packets if the number of those packets exceeds the threshold (configured by strapping during reset and eeprom settings) in a preset period of time. if the preset period expires it will then resume receiving broadcast or multicast packets until the threshold is reached. the options are 25 %, 12%, 6% or 3% of network line rate for the maximum broadcast/multicast receiving threshold or unlimited (feature off). downloaded from: http:///
august 2003 21 ks8995e ks8995e micrel mii interface operationthe mii (media independent interface) is specified by the ieee 802.3 committee and provides a common interface between physical layer and mac layer devices. the ks8995e mii behaves like a physical layer device. there are two distinct groups, one being for transmission and the other for receiving. the table below describes the signals used in this interface. mii signal description ks8995e signal mtxen transmit enable mtxen mtxer transmit error mtxer mtxd3 transmit data bit 3 mtxd[3] mtxd2 transmit data bit 2 mtxd[2] mtxd1 transmit data bit 1 mtxd[1] mtxd0 transmit data bit 0 mtxd[0] mtxc transmit clock mii_clk mcol collision detection mcol mcrs carrier sense mrxdv mrxdv receive data valid mrxdv mrxer receive error not used mrxd3 receive data bit 3 mrxd[3] mrxd2 receive data bit 2 mrxd[2] mrxd1 receive data bit 1 mrxd[1] mrxd0 receive data bit 0 mrxd[0] mrxc receive clock mii_clk table 1. mii signals this interface is a nibble wide data interface and therefore runs at 1/4 the network bit rate (not encoded). additional signalson the transmit side indicate when data is valid or when an error occurs during transmission. likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation there is a signal that indicate a collision has occurred during transmission. note that the signal mrxer is not provided on the mii interface for the ks8995e. normally this would indicate a receive error coming from the physical layer device, but since this port connects to a mac device it is not appropriate. if the connecting de vice has a mrxer pin, this should be tied low on the other device. downloaded from: http:///
ks8995e micrel ks8995e 22 august 2003 sni interface (7-wire) operationthe sni (serial network interface) is compatible with some controllers used for network layer protocol processing. ks8995e acts like a phy device to external controllers. this interface can be directly connected to these types of devices. the signals are divided into two groups, one being for transmission and the other being the receive side. the signals involved are describe d in the table below. sni signal description ks8995e sni signal ks8995e input/output txen transmit enable mtxen input txd serial transmit data mtxd[0] input txc transmit clock mii_clk output col collision detection mcol output crs carrier sense mrxdv output rxd serial receive data mrxd[0] output rxc receive clock mii_clk output table 2. sni signal this interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). an additional signal on t he transmit side indicates when data is valid. likewise, the receive side has an indicator that conveys when the data is valid.for half-duplex operation there is a signal that indicate a collision has occurred during transmission. 8995e improvements priority schemes the ks8995e can determine priority through three different means. the first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the dscp (tos) field in the ipv4 header. of course for the priority to be effective, the high and low priority queues must be enabled on the destination port or egress point. per port method general priority can be specified on a per port basis. in this type of priority all traffic from the specified input port is co nsidered high priority in the destination queue. this can be useful in ip phone applications mixed with other data types of traffic wher e the ip phone connects to a specific port. the ip phone traffic would be high priority (outbound) to the wide area network. theinbound traffic to the ip phone is all of the same priority to the ip phone. 802.1p method this method works well when used with ports that have mixed data and media flows. the inbound port examines the priority field in the tag and determines the high or low priority. priority profiles are setup in the priority classification control in the eeprom. ipv4 dscp method this is another per frame way of determining outbound priority. the dscp (differentiated services code point Crfc#2474) method uses the tos field in the ip header to determine high and low priority on a per code point basis. each fully decodedcode point can have either a high or low priority. a larger spectrum of priority flows can be defined with this larger code spa ce. more specific to implementation, the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and thesingular code that results is compared against the corresponding bit in the dscp register. if the register bit is a 1, the prio rity is high and if 0, the priority is low.other priority considerations when setting up the priority scheme, one should consider other available controls to regulate the traffic. one of these is prio rity control scheme (register 3 bits 7-6) which controls the interleaving of high and low priority frames. options allow from a 2:1 ratio up to a setting that sends all the high priority first. this setting controls all ports globally. another global feature is priority buffer reserve (register 5 bit 7). if this is set, there is a 12kb (10%) buffer dedicated to high priority traffic, otherwise if cleared the buffer is shared between all traffic. on an individual port basis there are controls that enable dscp, 802.1p, port based and high/low priority queues. these are contained in registers 3-7 bits 5-3 and 0. downloaded from: http:///
august 2003 23 ks8995e ks8995e micrel the table below briefly summarizes priority features. for more detailed settings see the eeprom register description. register(s) bit(s) global/port description general 3 7-6 global priority control scheme: transmit buffer high/low interleave control. 5 7 global priority buffer reserve: reserves 12kb of the buffer for high priority traffic. 3-7 0 port enable port queue split: splits the transmit queue on the desired port for high and low priority traffic. dscp priority 3-7 5 port enable port dscp: looks at dscp field in ip header to decide high or low priority. 23-30 7-0 global dscp priority points: fully decoded 64 bit register used to determine priority from dscp field (6 bits) in the ip header. 802.1p priority 3-7 4 port enable port 802.1p priority: uses the 802.1p priority tag (3 bits) to determine frame priority. 2 7-0 global priority classification: determines which tag values have high priority. per port priority 3-7 3 port enable port priority: determines which ports have high priority traffic. table 3. priority control vlan operationthe vlan s are setup by programming the vlan mask registers in the eeprom. the perspective of the vlan is from the input port and which output ports it sees directly through the switch. for example if port 1 only participated in a vlan with p orts 2 and 5 then one would set bits 1 and 4 in register 8 (port 1 vlan mask register). note that different ports can be setupindependently. an example of this would be where a router is connected to port 5 and each of the other ports would work autonomously. in this configuration ports 1 through 4 would only set the mask for port 5 and port 5 would set the mask for port s 1 through 4. in this way the router could see all ports and each of the other individual ports would only communicate with therouter. all multicast and broadcast frames adhere to the vlan configuration. unicast frame treatment is a function of register 5 bit 6. if this bit is set then unicast frames only see ports within their vlan. if this bit is cleared unicast frames can traverse vlans. vlan tags can be added or removed on a per port basis. further, there are provisions to specify the tag value to be insertedon a per port basis. the table below briefly summarizes vlan features. for more detailed settings see eeprom memory map section. register(s) bit(s) global/port description 3-7 2 port insert vlan tags: if specified, will add vlan tags to frames without existing tags 3-7 1 port strip vlan tags: if specified, will remove vlan tags from frames if they exist 5 6 global vlan enforcement: allows unicast frames to adhere or ignore the vlan configuration 8-12 4-0 port vlan mask registers: allows configuration of individual vlan grouping. note reserved bit in each of the registers (sliding position). 13-22 7-0 port vlan tag insertion values: specifies the vlan tag to be inserted if enabled (see above) table 4. vlan control downloaded from: http:///
ks8995e micrel ks8995e 24 august 2003 other programmable featuresother available features include port aggregation, frame length enforcement and broadcast storm protection. additionally the mac source address can be programmed as used in flow control frames. port aggregation is used when additional bandwidth is desired to a specific path or end unit. this can turn a 100mb path into either a 200mb or 400mb path. this allows high throughput where needed. the frame length enforcement control allows filtering of frames that exceed 1518 bytes for non-vlan or 1522 bytes for vlan. the maximum frame size is capped at 1536 bytes. of course minimum frame size of 64 bytes is always enforced. the broadcast storm control prevents excessive broadcast frames from bogging down the switch. broadcast frames are restricted to their vlan and can further be controlled down to as low as 3% of the traffic. the maximum level for broadcast frames is at 25% when the broadcast storm control is enabled. the feature is generally enabled by strapping led[3][2] at reset time. the table below briefly summarizes other programmable features. for more detailed settings see eeprom memory map section. register(s) bit(s) global/port description 4 7-6 global port trunk control: allows ports to be aggregated together for higher throughput. 6 6 global maximum frame length enforcement: allows frames up to 1536 bytes to be passed. 7 7-6 global broadcast storm protection: allows as much as 25% to as little as 3% broadcast frames. 31-36 7-0 global station mac address: used as source address for mac control frames as used in full duplex flow control mechanisms. table 5. misc control eeprom operationthe eeprom interface utilizes 2 pins that provide a clock and a serial data path. as part of the initialization sequence, the ks8995e reads the contents of the eeprom and loads the values into the appropriate registers. note that the first two bytes in the eeprom must be 55 and 95 respectively for the loading to occur properly. if these first two values are not correct, all other data will be ignored.data start and stop conditions are signaled on the data line as a state transition during clock high time. a high to low transi tion indicates start of data and a low to high transition indicates a stop condition. the actual data that traverses the serial linechanges during the clock low time. the ks8995e eeprom interface is compatible with the atmel at24c01a part. further timing and data sequences can be found in the atmel at24c01a specification. compatibility with the ks8995 the ks8995e supports the same i/o strapping and i/o configuration as the ks8995 for existing designs. two i/o definition changes were necessary to provide for the eeprom interface. this effects pins 56 and 57 and relates to the switch core clocking. switch core clocking is now fixed at 42mhz and is no longer adjustable. downloaded from: http:///
august 2003 25 ks8995e ks8995e micrel eeprom memory map register bit(s) description default (chip) value 0 7-0 signature byte 1. value = 55 0x55 1 7-0 signature byte 2. value = 95 0x95 priority classification control - 802.1p tag field 2 7 1 = state 111 is high priority 0 0 = state 111 is low priority 2 6 1 = state 110 is high priority 0 0 = state 110 is low priority 2 5 1 = state 101 is high priority 0 0 = state 101 is low priority 2 4 1 = state 100 is high priority 0 0 = state 100 is low priority 2 3 1 = state 011 is high priority 0 0 = state 011 is low priority 2 2 1 = state 010 is high priority 0 0 = state 010 is low priority 2 1 1 = state 001 is high priority 0 0 = state 001 is low priority 2 0 1 = state 000 is high priority 0 0 = state 000 is low priority control register 1 3 7-6 priority control scheme (all ports) 00 00 = transmit all high priority before any low priority01= transmit high and low priority at a 10:1 ratio 10 = transmit high and low priority at a 5:1 ratio 11 = transmit high and low priority at a 2:1 ratio 3 5 tos priority classification enable for port 1 0 1 = enable, 0 = disable 3 4 802.1p priority classification enable for port 1 0 1 = enable, 0 = disable 3 3 port based priority classification for port 1 0 1 = enable, 0 = disable 3 2 insert vlan tags for port 1 if non-existent 0 1 = enable, 0 = disable 3 1 strip vlan tags for port 1 if existent 0 1 = enable, 0 = disable 3 0 enable high and low output priority queues for port 1 0 1 = enable, 0 = disable control register 2 4 7-6 port trunk (link aggregation) control 00 00 = disable01 = ports 1 and 2 are trunked 10 = ports 1 and 2 are trunked, ports 3 and 4 are trunked 11 = ports 1, 2, 3, 4 are trunked 4 5 tos priority classification enable for port 2 0 1 = enable, 0 = disable 4 4 802.1p priority classification enable for port 2 0 1 = enable, 0 = disable 4 3 port based priority classification for port 2 0 1 = enable, 0 = disable downloaded from: http:///
ks8995e micrel ks8995e 26 august 2003 register bit(s) description default (chip) value 4 2 insert vlan tags for port 2 if non-existent 0 1 = enable, 0 = disable 4 1 strip vlan tags for port 2 if existent 0 1 = enable, 0 = disable 4 0 enable high and low output priority queues for port 2 0 1 = enable, 0 = disable control register 3 5 7 priority buffer reserve for high priority traffic 0 1 = reserve 12kb of buffer space for high priority 0 = none reserved 5 6 vlan enforcement 0 1 = all unicast frames adhere to vlan configuration 0 = unicast frames ignore vlan configuration 5 5 tos priority classification enable for port 3 0 1 = enable, 0 = disable 5 4 802.1p priority classification enable for port 3 0 1 = enable, 0 = disable 5 3 port based priority classification for port 3 0 1 = enable, 0 = disable 5 2 insert vlan tags for port 3 if non-existent 0 1 = enable, 0 = disable 5 1 strip vlan tags for port 3 if existent 0 1 = enable, 0 = disable 5 0 enable high and low output priority queues for port 3 0 1 = enable, 0 = disable control register 4 6 7 reserved 0 6 6 maximum frame length enforcement 1 1 = pass non-vlan frames between 64-1518 bytes and vlanframes between 64-1522 bytes 0 = pass any frame between 64-1536 bytes 6 5 tos priority classification enable for port 4 0 1 = enable, 0 = disable 6 4 802.1p priority classification enable for port 4 0 1 = enable, 0 = disable 6 3 port based priority classification for port 4 0 1 = enable, 0 = disable 6 2 insert vlan tags for port 4 if non-existent 0 1 = enable, 0 = disable 6 1 strip vlan tags for port 4 if existent 0 1 = enable, 0 = disable 6 0 enable high and low output priority queues for port 4 0 1 = enable, 0 = disable control register 5 7 7-6 broadcast storm protection control 00 00 = allow 25% broadcast frames01 = allow 12% broadcast frames 10 = allow 6% broadcast frames 11 = allow 3% broadcast frames 7 5 tos priority classification enable for port 5 0 1 = enable, 0 = disable downloaded from: http:///
august 2003 27 ks8995e ks8995e micrel register bit(s) description default (chip) value 7 4 802.1p priority classification enable for port 5 0 1 = enable, 0 = disable 7 3 port based priority classification for port 5 0 1 = enable, 0 = disable 7 2 insert vlan tags for port 5 if non-existent 0 1 = enable, 0 = disable 7 1 strip vlan tags for port 5 if existent 0 1 = enable, 0 = disable 7 0 enable high and low output priority queues for port 5 0 1 = enable, 0 = disable port 1 vlan mask register 8 7-5 reserved 000 8 4 port 5 inclusion 1 1 = port 5 in the same vlan as port 1 0 = port 5 not in the same vlan as port 1 8 3 port 4 inclusion 1 1 = port 4 in the same vlan as port 1 0 = port 4 not in the same vlan as port 1 8 2 port 3 inclusion 1 1 = port 3 in the same vlan as port 1 0 = port 3 not in the same vlan as port 1 8 1 port 2 inclusion 1 1 = port 2 in the same vlan as port 1 0 = port 2 not in the same vlan as port 1 8 0 reserved 1 port 2 vlan mask register 9 7-5 reserved 000 9 4 port 5 inclusion 1 1 = port 5 in the same vlan as port 2 0 = port 5 not in the same vlan as port 2 9 3 port 4 inclusion 1 1 = port 4 in the same vlan as port 2 0 = port 4 not in the same vlan as port 2 9 2 port 3 inclusion 1 1 = port 3 in the same vlan as port 2 0 = port 3 not in the same vlan as port 2 9 1 reserved 1 9 0 port 1 inclusion 1 1 = port 1 in the same vlan as port 2 0 = port 1 not in the same vlan as port 2 port 3 vlan mask register 10 7-5 reserved 000 10 4 port 5 inclusion 1 1 = port 5 in the same vlan as port 3 0 = port 5 not in the same vlan as port 3 10 3 port 4 inclusion 1 1 = port 4 in the same vlan as port 3 0 = port 4 not in the same vlan as port 3 10 2 reserved 1 downloaded from: http:///
ks8995e micrel ks8995e 28 august 2003 register bit(s) description default (chip) value 10 1 port 2 inclusion 1 1 = port 2 in the same vlan as port 3 0 = port 2 not in the same vlan as port 3 10 0 port 1 inclusion 1 1 = port 1 in the same vlan as port 3 0 = port 1 not in the same vlan as port 3 port 4 vlan mask register 11 7-5 reserved 000 11 4 port 5 inclusion 1 1 = port 5 in the same vlan as port 4 0 = port 5 not in the same vlan as port 4 11 3 reserved 1 11 2 port 3 inclusion 1 1 = port 3 in the same vlan as port 4 0 = port 3 not in the same vlan as port 4 11 1 port 2 inclusion 1 1 = port 2 in the same vlan as port 4 0 = port 2 not in the same vlan as port 4 11 0 port 1 inclusion 1 1 = port 1 in the same vlan as port 4 0 = port 1 not in the same vlan as port 4 port 5 vlan mask register 12 7-5 reserved 000 12 4 reserved 1 12 3 port 4 inclusion 1 = port 4 in the same vlan as port 5 0 = port 4 not in the same vlan as port 5 1 12 2 port 3 inclusion 1 = port 3 in the same vlan as port 5 0 = port 3 not in the same vlan as port 5 1 12 1 port 2 inclusion 1 = port 2 in the same vlan as port 5 0 = port 2 not in the same vlan as port 5 1 12 0 port 1 inclusion 1 = port 1 in the same vlan as port 5 0 = port 1 not in the same vlan as port 5 1 port 1 vlan tag insertion value registers 13 7-5 user priority [2:0] 000 13 4 cfi 0 13 3-0 vid [11:8] 0x0 14 7-0 vid [7:0] 0x00 port 2 vlan tag insertion value registers 15 7-5 user priority [2:0] 000 15 4 cfi 0 15 3-0 vid [11:8] 0x0 16 7-0 vid [7:0] 0x00 downloaded from: http:///
august 2003 29 ks8995e ks8995e micrel register bit(s) description default (chip) value port 3 vlan tag insertion value registers 17 7-5 user priority [2:0] 000 17 4 cfi 0 17 3-0 vid [11:8] 0x0 18 7-0 vid [7:0] 0x00 port 4 vlan tag insertion value registers 19 7-5 user priority [2:0] 000 19 4 cfi 0 19 3-0 vid [11:8] 0x0 20 7-0 vid [7:0] 0x00 port 5 vlan tag insertion value registers 21 7-5 user priority [2:0] 000 21 4 cfi 0 21 3-0 vid [11:8] 0x0 22 7-0 vid [7:0] 0x00 diff serv code point registers 23 7-0 dscp[63:56] 0x00 24 7-0 dscp[55:48] 0x00 25 7-0 dscp[47:40] 0x00 26 7-0 dscp[39:32] 0x00 27 7-0 dscp[31:24] 0x00 28 7-0 dscp[23:16] 0x00 29 7-0 dscp[15:8] 0x00 30 7-0 dscp[7:0] 0x00 station mac address registers (all ports - mac control frames only) 31 7-0 mac address [47:40] 0x00 32 7-0 mac address [39:32] 0x40 33 7-0 mac address [31:24] 0x05 34 7-0 mac address [23:16] 0x43 35 7-0 mac address [15:8] 0x5e 36 7-0 mac address [7:0] 0xfe note. the mac address is reset to the value in the above table, but can set to any value via the eeprom interface. this mac address is used as the source address in mac control frames that execute flow control between link peers. downloaded from: http:///
ks8995e micrel ks8995e 30 august 2003 absolute maximum ratings (note 1) supply voltage (v ddar, v ddap, v ddc ) ............................. C 0.5v to +2.4v (v ddat, v ddio ) ........................................ C 0.5v to +4.0v input voltage ............................................... C 0.5v to +4.0v output voltage ............................................ C 0.5v to +4.0v lead temperature (soldering, 10 sec.) ..................... 270 c storage temperature (t s ) ....................... C55 c to +150 c operating ratings (note 2) supply voltage (v in ) ........................... +2.375v to +2.625v ambient temperature (t a ) ........................... C0 c to +70 c package thermal resistance (note 3) pqfp ( ja ) no air flow ................................. 42.91 c/w electrical characteristics (note 4) v dd = 2.5v to 2.75v; t a = 0 c to +70 c; unless noted. symbol parameter condition min typ max units v dd supply voltage 2.375 2.5 2.625 v total supply current (including tx output driver current) i dd1 normal 100basetx 0.5 a i dd2 normal 10baset 0.7 a ttl inputsv ih input high voltage v dd (i/o) C 0.8 v v il input low voltage 0.8 v i in input current v in = gnd ~ v dd C 10 10 a ttl outputsv oh output high voltage i oh = C4ma v dd (i/o) C 0.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a 100basetx receive v b rxp/rxm input bias voltage 1.9 v 100basetx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 50 from each output to v dd 0.95 1.05 v v imb output voltage imbalance 50 from each output to v dd 2% t r , t t rise/fall time 35 n s rise/fall time imbalance 0.5 ns duty cycle distortion 0.5 ns overshoot 5% v set reference voltage of iset 0.75 v output jitters peak-to-peak 0.7 1.4 ns 10basetx receive v sq squelch threshold 5mhz square wave 400 mv note 1. exceeding the absolute maximum rating may damage the device. note 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate logic voltage level (ground to v dd ). note 3. no hs (heat spreader) in package. note 4. specification for packaged product only. downloaded from: http:///
august 2003 31 ks8995e ks8995e micrel symbol parameter condition min typ max units 10basetx transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 50 from each output to v dd 2.3 v jitters added 50 from each output to v dd 3.5 ns rise/fall time 25 ns downloaded from: http:///
ks8995e micrel ks8995e 32 august 2003 timing diagrams ts th tcyc scl sda input timing figure 2. eeprom input timing symbol parameter min typ max units t cyc clock cycle 12288 ns t s set-up time 10 ns t h hold time 5n s table 6. eeprom input timing parameters tcyc scl sda output timing tov figure 3. eeprom output timing symbol parameter min typ max units t cyc clock cycle 12288 ns t ov output valid 3056 3072 3088 ns table 7. eeprom output timing parameters downloaded from: http:///
august 2003 33 ks8995e ks8995e micrel ts th tcyc mii_clk mtxd[0], mtxen input timing figure 4. sni (7-wire) input timing symbol parameter min typ max units t cyc clock cycle 100 ns t s set-up time 10 ns t h hold time 0n s table 8. sni (7-wire) input timing parameters tcyc mii_clk mrxd[0], mrxdv, mcol output timing tov figure 5. sni (7-wire) output timing symbol parameter min typ max units t cyc clock cycle 100 ns t ov output valid 036n s table 9. sni (7-wire) output timing parameters downloaded from: http:///
ks8995e micrel ks8995e 34 august 2003 uplink module mac ks8995s port 5 acting like a phy mii clk mtxd [ 3:0 ] mtxen mtxer ts th tcyc mii_clk mtxd[3:0] mtxen mtxer figure 6. reverse mii timingCreceive data from mii symbol parameter min typ max units t cyc clock cycle (100baset) 40 ns (10baset) 400 t s set-up time 10 ns t h hold time 0n s table 10. reverse mii timing C receive data from mii parameters downloaded from: http:///
august 2003 35 ks8995e ks8995e micrel uplink module mac ks8995s port 5 acting like a phy mii clk mrxd [ 3:0 ] mrxen tcyc mii_clk mrxd[3:0] mrxdv tov figure 7. reverse mii timing C transmit data to mii symbol parameter min typ max units t cyc clock cycle (100baset) 40 ns (10baset) 400 t ov output valid 18 25 28 ns table 11. reverse mii timing C transmit data to mii parameters downloaded from: http:///
ks8995e micrel ks8995e 36 august 2003 reference circuitsee i/o description section for pull-up/pull-down and float information. ks8995e led pin 2.5 v reference circuits for unmanaged programming through led ports ks8995e led pin 2.5 v pull down pull-up ks8995e led pin 2.5 v float pull-down 220 220 220 1k 10k figure 8. unmanaged programming circuit the following transformer vendors provide pin-to-pin compatible p arts for micrels device: magnetics vendor transformer only integrated rj4 & 5 transformer quad single transformer hb826-2 hb726-1 1x8 (4-port) rjg4-726 www.trans-power.com 1x5 (5-port) rjg5-726 pulse h1164 h1102 www.pulse.com bel fuse 558-5999-q9 s558-5999-u7 ycl ph406466 pt163020 table 12. magnetic vendor list downloaded from: http:///
august 2003 37 ks8995e ks8995e micrel 4b/5b codingin 100basetx and 100basefx the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4b/5b code. the extra code space is required to code type 4b code 5b code value data 0000 11110 data value 0 0001 01001 data value 1 0010 10100 data value 2 0011 10101 data value 3 0100 01010 data value 4 0101 01011 data value 5 0110 01110 data value 6 0111 01111 data value 7 1000 10010 data value 8 1001 10011 data value 9 1010 10110 data value a 1011 10111 data value b 1100 11010 data value c 1101 11011 data value d 1110 11100 data value e 1111 11101 data value f control not defined 11111 idle 0101 11000 start delimiter part 1 0101 10001 start delimiter part 2 not defined 01101 end delimiter part 1 not defined 00111 end delimiter part 2 not defined 00100 transmit error invalid not defined 00000 invalid code not defined 00001 invalid code not defined 00010 invalid code not defined 00011 invalid code not defined 00101 invalid code not defined 00110 invalid code not defined 01000 invalid code not defined 01100 invalid code not defined 10000 invalid code not defined 11001 invalid code table 13. 4b/5b coding encode extra control (frame delineation) points. it is also usedto reduce run length as well as supply sufficient transitions for clock recovery. the table below provides the translation for the 4b/5b coding. downloaded from: http:///
ks8995e micrel ks8995e 38 august 2003 mlt3 coding for 100basetx operation the nrzi (non-return to zero invert on ones) signal is line coded as mlt3. the net result of using mlt3 is to reduce the emi (electro magnetic inter- ference) of the signal over twisted pair media. in nrzi coding, the level changes from high to low or low to high for every 1 bit. for a 0 bit there is no transition. mlt3 line coding transitions through three distinct levels. for every transitionof the nrzi signal the mlt3 signal either increments or decrements depending on the current state of the signal. for instance if the mlt3 level is at its lowest point the next twonrzi transitions will change the mlt3 signal initially to the middle level followed by the highest level (second nrzi transition). on the next nrzi change, the mlt3 level will decrease to the middle level. on the following transition of the nrzi signal the mlt3 level will move to the lowest level where the cycle repeats. the diagram below describes the level changes. note that in the actual 100basetx circuit there is a scrambling circuit and that scrambling is not shown in this diagram. a 3 8 e 9 4 t3 r3 i1 i11010 0011 1000 1110 1001 0100 uuuu uuuu uuuu uuuu 10110101011001011100100110101001101001111111111111 hex valuebinary 4b binary 5b nrz nrzimlt3 figure 9. mlt3 coding field octect length description preamble/sfd 8 preamble and start of frame delimiter da 6 48-bit destination mac address sa 6 48-bit source mac address 802.1p tag 4 vlan and priority tag (optional) length 2 frame length protocol/data 46 to 1500 higher layer protocol and frame data frame crc 4 32-bit cyclical redundancy check esd 1 end of stream delimiter idle variable inter frame idles table 14. mac frame for 802.3 the mac (media access control) fields are described in the table below. downloaded from: http:///
august 2003 39 ks8995e ks8995e micrel 802.1q vlan and 802.1p priority framethe 3-bit of 802.1p priority is embedded into the 802.1q vlan frame as described below: 802.1q vlan 802.1q vlan 802.1p priority ds typ dat fcs 66 2 46 - 1500 4 vlan tag control 22 (bit) protocol id priorit cfi vlan identifier 16 12 3 figure 10. 802.1q and 802.1p frame format downloaded from: http:///
ks8995e micrel ks8995e 40 august 2003 selection of isolation transformer (note 1) one simple 1:1 isolation transformer is needed at the line interface. an isolation transformer with integrated common-modechoke is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. characteristics name value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma leakage inductance (max.) 0.4 h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms note 1. the ieee 802.3u standard for 100basetx assumes a transformer loss of 0.5db. for the transmit line transformer, insertion loss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. selection of reference crystalan oscillator or crystal with the following typical characteristics is recommended. characteristics name value units frequency 25.00000 mhz frequency tolerance (max.) 100 ppm jitter (max.) 150 ps(pk-pk) downloaded from: http:///
august 2003 41 ks8995e ks8995e micrel package information 128-pin pqfp (pq) micrel, inc. 1849 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 web http://www.micrel.com the information furnished by micrel in this datasheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2003 micrel, incorporated. downloaded from: http:///

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